Semiconductor devices in the form of integrated circuit chips (ICs) must typically be mounted on a flat surface such as a printed circuit board when they are incorporated into a product such as a computer or cellular phone. No surface-mount semiconductor packaging technology exists today that is capable of meeting the needs of the next-generation of discrete power semiconductor devices and ICs.
Such surface-mount power packages should include at least the following features:
1. A low electrical resistance. PA1 2. The capability of shunting current and reducing the lateral resistance in a device's metal interconnect. PA1 3. A low thermal resistance. PA1 4. The capability of achieving high currents vertically (through backside) or laterally (topside). PA1 5. High manufacturability. PA1 6. A low intrinsic material cost. PA1 7. A low manufacturing cost. PA1 8. Reliable operation in power applications. PA1 9. The ability to facilitate at least three (and preferably more) isolated connections to the semiconductor. PA1 10. A low profile (height) and small footprint.
Power semiconductor devices and ICs come in two types, those that conduct high currents because they exhibit low on-state voltage drops (and hence low power dissipation) and those that conduct "high" currents because they dissipate large amounts of power. Because of the varied use, construction, and operation of such power devices, the first two features listed (i.e. low electrical resistance) can be achieved in lieu of the third feature (low thermal resistance), but ideally one package should offer both low electrical and thermal resistance.
The fourth feature, a high current flow laterally or vertically, specifies that a power package should ideally be applicable to both lateral and vertical power devices, but at least one of the two orientations should be high current capable.
Of course, the package must be highly manufacturable since power transistors are used in high quantities, billions of units yearly, worldwide. Any intrinsic manufacturing repeatability or yield problem would have dire consequences for the supplier and likely the user of such devices.
Another feature is low cost, including the package material cost and the cost of its manufacture. Of these, the material cost is fundamental since the prices of certain materials such as gold wire, plastic molding, copper leadframes, etc., are based on the world market for the raw material and cannot be substantially changed through simple increases in semiconductor product volume. Package designs using smaller amounts of material are inherently cheaper to produce.
The reliability of a package in a power application means it must survive operating conditions commonly encountered in power device use, such as current spikes, higher ambient temperatures than normally encountered, significant self heating, thermal shock from repeated thermal transients, etc. Repeated pulses of current or heating can provoke fatigue-related failures, particularly at metallurgical junctions and interfaces. Fewer interfaces are preferable.
Two-terminal packages are needed for diodes, transient suppressors, and fuses, while packages supporting at least three connections are useful for discrete transistors. Four connections up to eight connections are extremely valuable for a variable of smarter power semiconductor components. Beyond eight distinct connections, the use of such power package technology is concentrated on power integrated circuits.
Low profile surface mount packages, while not universally required, make it convenient for PC board manufacturing since power devices packaged in low profile packages have the same characteristics of other ICs on the same board and hence avoid the need for special handling. In some cases like battery packs, PCMCIA cards and cell phones, the low profile package may be crucial in meeting a critical thickness in the final end product.
Small footprint is generally a matter of overall product size, especially in portable electronics where size is an important consumer buying criteria--the smaller the better.
In a related consideration, the smaller the package footprint is on the board and the larger the semiconductor die it contains, the performance for a given size is greater.
While these goals may seem obvious, the fact is that today's power semiconductor-packaging technology does not meet these needs adequately, cost effectively, and in some cases, at all. Many of the disadvantages of the conventional packages are a consequence of the use of bond wires. Bond wires contribute added resistance and are ineffective in their conduction of heat, especially wires that are connected to the topside source pad in a power MOSFET, insulated gate bipolar transistor, or bipolar transistor. Several firms have attempted to develop a bond-wireless connection to the gate, but these attempts have been unsuccessful and the firms have had to revert to a wire-bonded gate connection.
One such attempt at a process flow for fabricating a power MOSFET containing a bond-wireless source connection combined with a gate bond wire is shown in FIG. 1A. In this flow, an epoxy die attach (and partial cure) between the die and the top leadframe is then followed by flipping the die over and attaching it via epoxy to the bottom leadframe. Because of the torque applied by the tie bars to the die attach portion of the leadframe, maintaining a uniform interfacial epoxy layer is difficult at best. Moreover, in this flow, wire bonding must occur after the bond-wireless die-attach. After the wire-bond is made, molding, trimming and forming still must occur.
FIG. 1B illustrates a top leadframe 440 epoxy-attached to die 442. The curved-metal "camel hump" leadframe 440 (i.e. the step-up and down-set leadframe) makes a uniform die attach operation difficult. After die attach, the plan view of FIG. 1C illustrates the bond-wireless portion 444 of the top leadframe 440 and the shorter "diving board" piece 446 used for wire bonding the gate. Even with a tie bar tied to one side, holding leadframe 440 stable during wire bonding is difficult.
After the top leadframe 440 is attached to the die 442, the bottom leadframe 448 is die-attached using conductive epoxy, as shown in the cross-sectional view of FIG. 1D and the plan view of FIG. 1E. Controlling the torque and pressure during die attach and curing is critical to a reliable product. The gate lead 446 is then wired-bonded, using a bonding wire 450, as shown in the perspective drawing of FIG. 1F. Mixing bonding wire and bond-wireless methods in the same package has a disadvantage in cost since the die-leadframe or die-strap assembly must be moved to a different machine to perform wire bonding. Handling the product takes time and costs money. In fact, this method has so many problems in achieving manufacturability that it may never be used commercially and may be abandoned altogether despite years of investment within the industry. Die-cracking, variable on-resistance, and on-resistance that changes during operation or burn-in are all symptomatic of this approach.
Notice that gate lead 446 is mechanically analogous to a diving board with little support of its free end during wire-bonding. Its movement makes the quality of the gate bond 452 questionable and variable. FIG. 1G shows another perspective drawing after plastic molding (shown as a dotted line 454). The asymmetry of the design renders manufacturing of this approach challenging and irreproducible.
Another approach is shown in the flow diagram of FIG. 2A. In this approach, the die is first attached to a copper strap layer to form a die and strap assembly, then subsequently the die and strap assembly is attached to a conventional leadframe. After this second attachment, the part still must be wire bonded to connect the gate of the device. Thereafter the structure is molded, trimmed and formed.
In FIG. 2B, again a camel hump piece of metal, in this case the "strap" 460 is aligned to the die 462. The strap 460 has a uniform width (see FIG. 2C) and therefore must be positioned so as to not cover the gate bonding pad 464 (see FIG. 2E) yet still contact the source. Strap 460 is shown in the cross-sectional view of FIG. 2D and the plan view of FIG. 2E as a source lead epoxy-attached to die 462 to form a die and strap assembly 461. It is critical that bottom surfaces of the foot 466 of the camel hump leadframe 460 and the die 462 be perfectly coplanar to avoid problems later in the process.
The bottom leadframe 470, shown in the cross-sectional view of FIG. 2F and the plan view in FIG. 2G, looks like a ordinary leadframe. Note that while lead frame is drawn as separate parts in FIGS. 2F-2R, in reality the parts are connected by a tie bar (not shown). Leadframe 470 is typically flat before it is attached to the die, although conceivably it could be pre-formed (i.e., already bent), which makes it even more difficult to handle.
In FIGS. 2H and 2I, the die and strap assembly 461, comprising the die 462 and copper strap 460, is aligned to the bottom leadframe 470, which is coated with epoxy "dots" 472. At this point, the epoxy dots 472 have no correspondence with surface features of the die, such as the gate pad 464. FIG. 2J is a view of the die and strap assembly 461 pushed onto the bottom leadframe 470, taken at cross-section J--J shown in FIG. 2I. As is evident, the coplanarity of the bottom surfaces of die 460 and the foot 466 of strap 460 are crucial in achieving two good, low-resistance epoxy joints simultaneously, the one under the die 460 and the other under the foot 466. Since the second joint is of limited area, this region contributes to an increased resistance compared to the three-terminal bond-wireless package shown in FIG. 1G. A view of the gate bonding area, taken at cross-section K--K in FIG. 2I, is shown in FIG. 2K.
After squeezing the epoxy by pressure, the epoxy should ideally redistribute evenly across the bottom of the metal strap and under the die as shown in FIG. 2L. Since the assembly is asymmetrical, however, uniform pressure is difficult to achieve reproducibly. As shown in the cross-sectional view of FIG. 2M and the plan view of FIG. 2N, a wire bond 480 is then made, followed by injection molding to form the plastic capsule 482 shown in FIGS. 2O and 2P.
Clearly the number of epoxy layers carrying high currents is greater than other packaging approaches--three in the design shown in FIG. 2Q, i.e., epoxy layers 484, 486 and 488. An option to introduce a heat sink 492 under the leadframe 470, as shown in FIG. 2R involves another epoxy layer 490. The design relies completely on the epoxy layer 490 to hold the heat sink 492 against the leadframe 470, without any mechanism to "lock" it in place. Furthermore, this design has the disadvantage that the many leads attached to the die pad and to the heat sink are all shorted together. The leads are in essence "wasted" because the heat sink is capable of carrying current without them.
Again the asymmetry of the design, especially during the many epoxy die attach steps, make the high volume manufacturability of this design suspect. Clearly, the large number of processing steps makes it expensive. The non-planar surface of the split leadframe (i.e. the leadframe comprising gate and source connections) is especially problematic since any downset exacerbates the coplanarity problem during top-side die attach.
In both attempts at bond-wireless techniques shown above, the gate pad must be attached electrically to the lead frame via bond wires rather than through a bond-wireless connection, ideally made at the same time as the source connection. The reason bond-wireless gate contacts have been unsuccessful is the lack of coplanarity between the gate and source leads. FIGS. 3A-3H illustrate the problem of coplanarity in three-terminal bond-wireless packaging. In FIG. 3A, a downset leadframe 402 and a silicon die 404 (with conductive epoxy dots 406 applied) are aligned and brought in contact as in FIG. 3B. Ideally constant pressure and minimal torque will squeeze both the gate lead 408 (the thin isolated lead) and the wider source metal 410 onto the die surface with equal force. But in fact it is difficult to guarantee that attach surfaces of the two leads 408 and 410 are coplanar, meaning at the same level. It is easy for the tie bar (not shown) to bend a small amount so that the attach surface of the gate lead 408 may, for example, be located slightly above the attach surface of the source lead 410. As shown in FIG. 3C, the consequence of this coplanarity problem is the gate lead 408 does not press onto the die 404 with sufficient force to redistribute the epoxy. As a result the gate lead 408 will exhibit a poor (or no) contact to the gate pad 412 (shown in FIG. 3A).
To further clarify this issue, FIG. 3D illustrates a downset lead 414 pressed properly onto the epoxy interlayer 416 to make good contact with a pad 418. In FIG. 3E, the downset lead 420 is parallel to the surface of the pad 418 but never touches, resulting in open circuit and a failed device. In FIG. 3F, the lead 422 is twisted touching only on its heal while in FIG. 3G, only the toe of lead 424 touches epoxy 416. In FIG. 3H lead 426 barely touches the epoxy 416, but the contact is so light that it does not redistribute the epoxy 416 properly, resulting in a poor electrical contact.
Another problem that occurs in bond-wireless packages is short-circuiting between adjacent leads as a result of the spreading of the liquid epoxy or solder used to make the die-leadframe attachment. As shown in the cross section of FIG. 4A, the epoxy 430 is squeezed with too much force (or too much epoxy was applied), resulting in a lateral short between the source leadframe 432 and the gate leadframe 434, shown in plan view in FIG. 4B.
Another problem occurs particularly with packages for vertical planar or trench-gated DMOSFETs. Most of the top surface of the device is covered by a source metal layer, while the gate pad is electrically isolated from the source metal, typically by a gap 2 to 15 .mu.m wide. The outer edge of the top surface typically includes a metal ring shorted to the drain on the bottom surface, referred to as an equipotential ring or EQR, primarily introduced for purposes of achieving improved reliability against ionic migration. This outer ring is a source of risk for an accidental short between the source or gate connections during assembly. The silicon extends beyond this ring by another 20 to 70 .mu.m. The protruding silicon varies in dimension due to the sawing process when the wafer is cut into separate dice. This area of the die is also biased at the drain potential and may short to a source or gate connected bond wire during packaging.